mirror of https://github.com/minio/minio.git
463 lines
12 KiB
NASM
463 lines
12 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2015 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%ifidn __OUTPUT_FORMAT__, elf64
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%define WRT_OPT wrt ..plt
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%else
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%define WRT_OPT
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%endif
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%ifidn __OUTPUT_FORMAT__, macho64
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%define EC_ENCODE_DATA_SSE _ec_encode_data_sse
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%define EC_ENCODE_DATA_AVX _ec_encode_data_avx
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%define EC_ENCODE_DATA_AVX2 _ec_encode_data_avx2
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%define EC_ENCODE_DATA_BASE _ec_encode_data_base
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%define EC_ENCODE_DATA _ec_encode_data
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%define EC_ENCODE_DATA_UPDATE_BASE _ec_encode_data_update_base
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%define EC_ENCODE_DATA_UPDATE_SSE _ec_encode_data_update_sse
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%define EC_ENCODE_DATA_UPDATE_AVX _ec_encode_data_update_avx
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%define EC_ENCODE_DATA_UPDATE_AVX2 _ec_encode_data_update_avx2
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%define GF_VECT_MAD_BASE _gf_vect_mad_base
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%define GF_VECT_MAD_SSE _gf_vect_mad_sse
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%define GF_VECT_MAD_AVX _gf_vect_mad_avx
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%define GF_VECT_MAD_AVX2 _gf_vect_mad_avx2
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%define GF_VECT_MUL_SSE _gf_vect_mul_sse
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%define GF_VECT_MUL_AVX _gf_vect_mul_avx
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%define GF_VECT_MUL_BASE _gf_vect_mul_base
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%define GF_VECT_MUL _gf_vect_mul
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%define GF_VECT_DOT_PROD_SSE _gf_vect_dot_prod_sse
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%define GF_VECT_DOT_PROD_AVX _gf_vect_dot_prod_avx
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%define GF_VECT_DOT_PROD_AVX2 _gf_vect_dot_prod_avx2
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%define GF_VECT_DOT_PROD_BASE _gf_vect_dot_prod_base
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%define GF_VECT_DOT_PROD _gf_vect_dot_prod
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%else
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%define EC_ENCODE_DATA_SSE ec_encode_data_sse
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%define EC_ENCODE_DATA_AVX ec_encode_data_avx
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%define EC_ENCODE_DATA_AVX2 ec_encode_data_avx2
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%define EC_ENCODE_DATA_BASE ec_encode_data_base
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%define EC_ENCODE_DATA ec_encode_data
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%define EC_ENCODE_DATA_UPDATE_BASE ec_encode_data_update_base
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%define EC_ENCODE_DATA_UPDATE_SSE ec_encode_data_update_sse
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%define EC_ENCODE_DATA_UPDATE_AVX ec_encode_data_update_avx
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%define EC_ENCODE_DATA_UPDATE_AVX2 ec_encode_data_update_avx2
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%define GF_VECT_MAD_BASE gf_vect_mad_base
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%define GF_VECT_MAD_SSE gf_vect_mad_sse
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%define GF_VECT_MAD_AVX gf_vect_mad_avx
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%define GF_VECT_MAD_AVX2 gf_vect_mad_avx2
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%define GF_VECT_MUL_SSE gf_vect_mul_sse
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%define GF_VECT_MUL_AVX gf_vect_mul_avx
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%define GF_VECT_MUL_BASE gf_vect_mul_base
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%define GF_VECT_MUL gf_vect_mul
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%define GF_VECT_DOT_PROD_SSE gf_vect_dot_prod_sse
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%define GF_VECT_DOT_PROD_AVX gf_vect_dot_prod_avx
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%define GF_VECT_DOT_PROD_AVX2 gf_vect_dot_prod_avx2
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%define GF_VECT_DOT_PROD_BASE gf_vect_dot_prod_base
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%define GF_VECT_DOT_PROD gf_vect_dot_prod
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%endif
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%include "ec_reg_sizes.asm"
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%ifidn __OUTPUT_FORMAT__, elf32
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[bits 32]
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%define def_wrd dd
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%define wrd_sz dword
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%define arg1 esi
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%define arg2 eax
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%define arg3 ebx
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%define arg4 ecx
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%define arg5 edx
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%else
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default rel
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[bits 64]
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%define def_wrd dq
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%define wrd_sz qword
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%define arg1 rsi
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%define arg2 rax
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%define arg3 rbx
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%define arg4 rcx
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%define arg5 rdx
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extern EC_ENCODE_DATA_UPDATE_SSE
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extern EC_ENCODE_DATA_UPDATE_AVX
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extern EC_ENCODE_DATA_UPDATE_AVX2
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extern GF_VECT_MUL_SSE
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extern GF_VECT_MUL_AVX
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extern GF_VECT_MAD_SSE
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extern GF_VECT_MAD_AVX
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extern GF_VECT_MAD_AVX2
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%endif
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extern GF_VECT_MUL_BASE
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extern EC_ENCODE_DATA_BASE
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extern EC_ENCODE_DATA_UPDATE_BASE
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extern GF_VECT_DOT_PROD_BASE
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extern GF_VECT_MAD_BASE
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extern GF_VECT_DOT_PROD_SSE
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extern GF_VECT_DOT_PROD_AVX
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extern GF_VECT_DOT_PROD_AVX2
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extern EC_ENCODE_DATA_SSE
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extern EC_ENCODE_DATA_AVX
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extern EC_ENCODE_DATA_AVX2
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section .data
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;;; *_mbinit are initial values for *_dispatched; is updated on first call.
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;;; Therefore, *_dispatch_init is only executed on first call.
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ec_encode_data_dispatched:
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def_wrd ec_encode_data_mbinit
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gf_vect_mul_dispatched:
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def_wrd gf_vect_mul_mbinit
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gf_vect_dot_prod_dispatched:
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def_wrd gf_vect_dot_prod_mbinit
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ec_encode_data_update_dispatched:
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def_wrd ec_encode_data_update_mbinit
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gf_vect_mad_dispatched:
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def_wrd gf_vect_mad_mbinit
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section .text
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;;;;
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; ec_encode_data multibinary function
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;;;;
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global EC_ENCODE_DATA:function
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ec_encode_data_mbinit:
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call ec_encode_data_dispatch_init
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EC_ENCODE_DATA:
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jmp wrd_sz [ec_encode_data_dispatched]
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ec_encode_data_dispatch_init:
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push arg1
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push arg2
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push arg3
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push arg4
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push arg5
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lea arg1, [EC_ENCODE_DATA_BASE WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea arg3, [EC_ENCODE_DATA_SSE WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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cmovne arg1, arg3
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and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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lea arg3, [EC_ENCODE_DATA_AVX WRT_OPT]
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jne _done_ec_encode_data_init
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mov arg1, arg3
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;; Try for AVX2
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xor ecx, ecx
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mov eax, 7
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cpuid
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test ebx, FLAG_CPUID1_EBX_AVX2
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lea arg3, [EC_ENCODE_DATA_AVX2 WRT_OPT]
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cmovne arg1, arg3
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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je _done_ec_encode_data_init
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lea arg1, [EC_ENCODE_DATA_SSE WRT_OPT]
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_done_ec_encode_data_init:
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pop arg5
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pop arg4
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pop arg3
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pop arg2
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mov [ec_encode_data_dispatched], arg1
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pop arg1
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ret
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;;;;
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; gf_vect_mul multibinary function
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;;;;
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global GF_VECT_MUL:function
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gf_vect_mul_mbinit:
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call gf_vect_mul_dispatch_init
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GF_VECT_MUL:
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jmp wrd_sz [gf_vect_mul_dispatched]
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gf_vect_mul_dispatch_init:
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push arg1
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%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
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lea arg1, [GF_VECT_MUL_BASE]
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%else
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push rax
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push rbx
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push rcx
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push rdx
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lea arg1, [GF_VECT_MUL_BASE WRT_OPT] ; Default
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mov eax, 1
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cpuid
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test ecx, FLAG_CPUID1_ECX_SSE4_2
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lea rbx, [GF_VECT_MUL_SSE WRT_OPT]
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je _done_gf_vect_mul_dispatch_init
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mov arg1, rbx
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;; Try for AVX
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and ecx, (FLAG_CPUID1_ECX_OSXSAVE | FLAG_CPUID1_ECX_AVX)
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cmp ecx, (FLAG_CPUID1_ECX_OSXSAVE | FLAG_CPUID1_ECX_AVX)
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jne _done_gf_vect_mul_dispatch_init
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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jne _done_gf_vect_mul_dispatch_init
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lea arg1, [GF_VECT_MUL_AVX WRT_OPT]
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_done_gf_vect_mul_dispatch_init:
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pop rdx
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pop rcx
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pop rbx
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pop rax
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%endif ;; END 32-bit check
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mov [gf_vect_mul_dispatched], arg1
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pop arg1
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ret
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;;;;
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; ec_encode_data_update multibinary function
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;;;;
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global EC_ENCODE_DATA_UPDATE:function
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ec_encode_data_update_mbinit:
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call ec_encode_data_update_dispatch_init
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EC_ENCODE_DATA_UPDATE:
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jmp wrd_sz [ec_encode_data_update_dispatched]
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ec_encode_data_update_dispatch_init:
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push arg1
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%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
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lea arg1, [ec_encode_data_update_base]
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%else
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push rax
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push rbx
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push rcx
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push rdx
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lea arg1, [EC_ENCODE_DATA_UPDATE_BASE WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [EC_ENCODE_DATA_UPDATE_SSE WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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cmovne arg1, rbx
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and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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lea rbx, [EC_ENCODE_DATA_UPDATE_AVX WRT_OPT]
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jne _done_ec_encode_data_update_init
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mov rsi, rbx
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;; Try for AVX2
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xor ecx, ecx
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mov eax, 7
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cpuid
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test ebx, FLAG_CPUID1_EBX_AVX2
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lea rbx, [EC_ENCODE_DATA_UPDATE_AVX2 WRT_OPT]
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cmovne rsi, rbx
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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je _done_ec_encode_data_update_init
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lea rsi, [EC_ENCODE_DATA_UPDATE_SSE WRT_OPT]
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_done_ec_encode_data_update_init:
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pop rdx
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pop rcx
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pop rbx
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pop rax
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%endif ;; END 32-bit check
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mov [ec_encode_data_update_dispatched], arg1
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pop arg1
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ret
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;;;;
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; gf_vect_dot_prod multibinary function
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;;;;
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global GF_VECT_DOT_PROD:function
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gf_vect_dot_prod_mbinit:
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call gf_vect_dot_prod_dispatch_init
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GF_VECT_DOT_PROD:
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jmp wrd_sz [gf_vect_dot_prod_dispatched]
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gf_vect_dot_prod_dispatch_init:
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push arg1
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push arg2
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push arg3
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push arg4
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|
|
push arg5
|
||
|
|
lea arg1, [GF_VECT_DOT_PROD_BASE WRT_OPT] ; Default
|
||
|
|
|
||
|
|
mov eax, 1
|
||
|
|
cpuid
|
||
|
|
lea arg3, [GF_VECT_DOT_PROD_SSE WRT_OPT]
|
||
|
|
test ecx, FLAG_CPUID1_ECX_SSE4_1
|
||
|
|
cmovne arg1, arg3
|
||
|
|
|
||
|
|
and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
|
||
|
|
cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
|
||
|
|
lea arg3, [GF_VECT_DOT_PROD_AVX WRT_OPT]
|
||
|
|
|
||
|
|
jne _done_gf_vect_dot_prod_init
|
||
|
|
mov arg1, arg3
|
||
|
|
|
||
|
|
;; Try for AVX2
|
||
|
|
xor ecx, ecx
|
||
|
|
mov eax, 7
|
||
|
|
cpuid
|
||
|
|
test ebx, FLAG_CPUID1_EBX_AVX2
|
||
|
|
lea arg3, [GF_VECT_DOT_PROD_AVX2 WRT_OPT]
|
||
|
|
cmovne arg1, arg3
|
||
|
|
;; Does it have xmm and ymm support
|
||
|
|
xor ecx, ecx
|
||
|
|
xgetbv
|
||
|
|
and eax, FLAG_XGETBV_EAX_XMM_YMM
|
||
|
|
cmp eax, FLAG_XGETBV_EAX_XMM_YMM
|
||
|
|
je _done_gf_vect_dot_prod_init
|
||
|
|
lea arg1, [GF_VECT_DOT_PROD_SSE WRT_OPT]
|
||
|
|
|
||
|
|
_done_gf_vect_dot_prod_init:
|
||
|
|
pop arg5
|
||
|
|
pop arg4
|
||
|
|
pop arg3
|
||
|
|
pop arg2
|
||
|
|
mov [gf_vect_dot_prod_dispatched], arg1
|
||
|
|
pop arg1
|
||
|
|
ret
|
||
|
|
|
||
|
|
;;;;
|
||
|
|
; gf_vect_mad multibinary function
|
||
|
|
;;;;
|
||
|
|
global GF_VECT_MAD:function
|
||
|
|
gf_vect_mad_mbinit:
|
||
|
|
call gf_vect_mad_dispatch_init
|
||
|
|
|
||
|
|
GF_VECT_MAD:
|
||
|
|
jmp wrd_sz [gf_vect_mad_dispatched]
|
||
|
|
|
||
|
|
gf_vect_mad_dispatch_init:
|
||
|
|
push arg1
|
||
|
|
%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
|
||
|
|
lea arg1, [gf_vect_mad_base]
|
||
|
|
%else
|
||
|
|
push rax
|
||
|
|
push rbx
|
||
|
|
push rcx
|
||
|
|
push rdx
|
||
|
|
lea arg1, [GF_VECT_MAD_BASE WRT_OPT] ; Default
|
||
|
|
|
||
|
|
mov eax, 1
|
||
|
|
cpuid
|
||
|
|
lea rbx, [GF_VECT_MAD_SSE WRT_OPT]
|
||
|
|
test ecx, FLAG_CPUID1_ECX_SSE4_1
|
||
|
|
cmovne arg1, rbx
|
||
|
|
|
||
|
|
and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
|
||
|
|
cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
|
||
|
|
lea rbx, [GF_VECT_MAD_AVX WRT_OPT]
|
||
|
|
|
||
|
|
jne _done_gf_vect_mad_init
|
||
|
|
mov rsi, rbx
|
||
|
|
|
||
|
|
;; Try for AVX2
|
||
|
|
xor ecx, ecx
|
||
|
|
mov eax, 7
|
||
|
|
cpuid
|
||
|
|
test ebx, FLAG_CPUID1_EBX_AVX2
|
||
|
|
lea rbx, [GF_VECT_MAD_AVX2 WRT_OPT]
|
||
|
|
cmovne rsi, rbx
|
||
|
|
|
||
|
|
;; Does it have xmm and ymm support
|
||
|
|
xor ecx, ecx
|
||
|
|
xgetbv
|
||
|
|
and eax, FLAG_XGETBV_EAX_XMM_YMM
|
||
|
|
cmp eax, FLAG_XGETBV_EAX_XMM_YMM
|
||
|
|
je _done_gf_vect_mad_init
|
||
|
|
lea rsi, [GF_VECT_MAD_SSE WRT_OPT]
|
||
|
|
|
||
|
|
_done_gf_vect_mad_init:
|
||
|
|
pop rdx
|
||
|
|
pop rcx
|
||
|
|
pop rbx
|
||
|
|
pop rax
|
||
|
|
%endif ;; END 32-bit check
|
||
|
|
mov [gf_vect_mad_dispatched], arg1
|
||
|
|
pop arg1
|
||
|
|
ret
|
||
|
|
|
||
|
|
%macro slversion 4
|
||
|
|
global %1_slver_%2%3%4
|
||
|
|
global %1_slver
|
||
|
|
%1_slver:
|
||
|
|
%1_slver_%2%3%4:
|
||
|
|
dw 0x%4
|
||
|
|
db 0x%3, 0x%2
|
||
|
|
%endmacro
|
||
|
|
|
||
|
|
;;; func core, ver, snum
|
||
|
|
slversion EC_ENCODE_DATA, 00, 03, 0133
|
||
|
|
slversion GF_VECT_MUL, 00, 02, 0134
|
||
|
|
slversion EC_ENCODE_DATA_UPDATE, 00, 02, 0212
|
||
|
|
slversion GF_VECT_DOT_PROD, 00, 02, 0138
|
||
|
|
slversion GF_VECT_MAD, 00, 01, 0213
|