mirror of https://github.com/minio/minio.git
267 lines
6.6 KiB
NASM
267 lines
6.6 KiB
NASM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright(c) 2011-2014 Intel Corporation All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; * Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; * Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in
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; the documentation and/or other materials provided with the
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; distribution.
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; * Neither the name of Intel Corporation nor the names of its
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; contributors may be used to endorse or promote products derived
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; from this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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%ifidn __OUTPUT_FORMAT__, elf64
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%define WRT_OPT wrt ..plt
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%else
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%define WRT_OPT
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%endif
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%ifidn __OUTPUT_FORMAT__, elf32
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[bits 32]
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%define def_wrd dd
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%define wrd_sz dword
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%define arg1 esi
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%else
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%include "reg-sizes.asm"
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default rel
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[bits 64]
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%define def_wrd dq
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%define wrd_sz qword
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%define arg1 rsi
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extern ec_encode_data_sse
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extern ec_encode_data_avx
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extern ec_encode_data_avx2
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extern gf_vect_mul_sse
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extern gf_vect_mul_avx
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extern gf_vect_dot_prod_sse
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extern gf_vect_dot_prod_avx
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extern gf_vect_dot_prod_avx2
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%endif
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extern gf_vect_mul_base
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extern ec_encode_data_base
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extern gf_vect_dot_prod_base
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section .data
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;;; *_mbinit are initial values for *_dispatched; is updated on first call.
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;;; Therefore, *_dispatch_init is only executed on first call.
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ec_encode_data_dispatched:
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def_wrd ec_encode_data_mbinit
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gf_vect_mul_dispatched:
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def_wrd gf_vect_mul_mbinit
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gf_vect_dot_prod_dispatched:
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def_wrd gf_vect_dot_prod_mbinit
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section .text
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;;;;
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; ec_encode_data multibinary function
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;;;;
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global ec_encode_data:function
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ec_encode_data_mbinit:
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call ec_encode_data_dispatch_init
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ec_encode_data:
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jmp wrd_sz [ec_encode_data_dispatched]
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ec_encode_data_dispatch_init:
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push arg1
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%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
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lea arg1, [ec_encode_data_base]
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%else
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push rax
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push rbx
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push rcx
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push rdx
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lea arg1, [ec_encode_data_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [ec_encode_data_sse WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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cmovne arg1, rbx
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and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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lea rbx, [ec_encode_data_avx WRT_OPT]
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jne _done_ec_encode_data_init
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mov rsi, rbx
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;; Try for AVX2
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xor ecx, ecx
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mov eax, 7
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cpuid
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test ebx, FLAG_CPUID1_EBX_AVX2
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lea rbx, [ec_encode_data_avx2 WRT_OPT]
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cmovne rsi, rbx
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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je _done_ec_encode_data_init
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lea rsi, [ec_encode_data_sse WRT_OPT]
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_done_ec_encode_data_init:
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pop rdx
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pop rcx
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pop rbx
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pop rax
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%endif ;; END 32-bit check
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mov [ec_encode_data_dispatched], arg1
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pop arg1
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ret
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;;;;
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; gf_vect_mul multibinary function
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;;;;
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global gf_vect_mul:function
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gf_vect_mul_mbinit:
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call gf_vect_mul_dispatch_init
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gf_vect_mul:
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jmp wrd_sz [gf_vect_mul_dispatched]
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gf_vect_mul_dispatch_init:
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push arg1
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%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
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lea arg1, [gf_vect_mul_base]
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%else
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push rax
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push rbx
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push rcx
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push rdx
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lea arg1, [gf_vect_mul_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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test ecx, FLAG_CPUID1_ECX_SSE4_2
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lea rbx, [gf_vect_mul_sse WRT_OPT]
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je _done_gf_vect_mul_dispatch_init
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mov arg1, rbx
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;; Try for AVX
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and ecx, (FLAG_CPUID1_ECX_OSXSAVE | FLAG_CPUID1_ECX_AVX)
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cmp ecx, (FLAG_CPUID1_ECX_OSXSAVE | FLAG_CPUID1_ECX_AVX)
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jne _done_gf_vect_mul_dispatch_init
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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jne _done_gf_vect_mul_dispatch_init
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lea arg1, [gf_vect_mul_avx WRT_OPT]
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_done_gf_vect_mul_dispatch_init:
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pop rdx
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pop rcx
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pop rbx
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pop rax
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%endif ;; END 32-bit check
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mov [gf_vect_mul_dispatched], arg1
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pop arg1
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ret
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;;;;
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; gf_vect_dot_prod multibinary function
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;;;;
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global gf_vect_dot_prod:function
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gf_vect_dot_prod_mbinit:
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call gf_vect_dot_prod_dispatch_init
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gf_vect_dot_prod:
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jmp wrd_sz [gf_vect_dot_prod_dispatched]
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gf_vect_dot_prod_dispatch_init:
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push arg1
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%ifidn __OUTPUT_FORMAT__, elf32 ;; 32-bit check
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lea arg1, [gf_vect_dot_prod_base]
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%else
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push rax
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push rbx
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push rcx
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push rdx
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lea arg1, [gf_vect_dot_prod_base WRT_OPT] ; Default
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mov eax, 1
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cpuid
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lea rbx, [gf_vect_dot_prod_sse WRT_OPT]
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test ecx, FLAG_CPUID1_ECX_SSE4_1
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cmovne arg1, rbx
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and ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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cmp ecx, (FLAG_CPUID1_ECX_AVX | FLAG_CPUID1_ECX_OSXSAVE)
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lea rbx, [gf_vect_dot_prod_avx WRT_OPT]
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jne _done_gf_vect_dot_prod_init
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mov rsi, rbx
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;; Try for AVX2
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xor ecx, ecx
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mov eax, 7
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cpuid
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test ebx, FLAG_CPUID1_EBX_AVX2
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lea rbx, [gf_vect_dot_prod_avx2 WRT_OPT]
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cmovne rsi, rbx
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;; Does it have xmm and ymm support
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xor ecx, ecx
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xgetbv
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and eax, FLAG_XGETBV_EAX_XMM_YMM
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cmp eax, FLAG_XGETBV_EAX_XMM_YMM
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je _done_gf_vect_dot_prod_init
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lea rsi, [gf_vect_dot_prod_sse WRT_OPT]
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_done_gf_vect_dot_prod_init:
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pop rdx
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pop rcx
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pop rbx
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pop rax
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%endif ;; END 32-bit check
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mov [gf_vect_dot_prod_dispatched], arg1
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pop arg1
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ret
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%macro slversion 4
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global %1_slver_%2%3%4
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global %1_slver
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%1_slver:
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%1_slver_%2%3%4:
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dw 0x%4
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db 0x%3, 0x%2
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%endmacro
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;;; func core, ver, snum
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slversion ec_encode_data, 00, 02, 0133
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slversion gf_vect_mul, 00, 02, 0134
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slversion gf_vect_dot_prod, 00, 01, 0138
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